Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures

ABSTRACT

Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.14/489,798, filed Sep. 18, 2014, the disclosure of which is herebyincorporated herein in its entirety by this reference.

TECHNICAL FIELD

Embodiments of the present disclosure relate to methods that may be usedto fabricate n-type metal-oxide-semiconductor (NMOS) field effecttransistors and p-type metal-oxide-semiconductor (PMOS) field effecttransistors having different stress states in a common layer on asemiconductor substrate, and to semiconductor structures and devicesfabricated using such methods.

BACKGROUND

Semiconductor devices such as microprocessors and memory devices employsolid state transistors as a basic, primary operational structure of theintegrated circuits thereof. One type of transistor commonly employed insemiconductor structures and devices is the field effect transistor(FET), generally includes a source contact, a drain contact, and one ormore gate contacts. A semiconductive channel region extends between thesource contact and the drain contact. One or more pn junctions aredefined between the source contact and the gate contact. The gatecontact is located adjacent at least a portion of the channel region,and the conductivity of the channel region is altered by the presence ofan electrical field. Thus, an electrical field is provided within thechannel region by applying a voltage to the gate contact. Thus, forexample, electrical current may flow through the transistor from thesource contact to the drain contact through the channel region when avoltage is applied to the gate contact, but may not flow through thetransistor from the source contact to the drain contact in the absenceof an applied voltage to the gate contact.

Recently, field-effect transistors (FETs) have been developed thatemploy discrete, elongated channel structures referred to as “fins.”Such a transistor is often referred to in the art as a “finFET.” Manydifferent configurations of finFETs have been proposed in the art.

The elongated channel structures or fins of a finFET comprise asemiconductor material that may be doped either n-type or p-type. It hasalso been demonstrated that the conductivity of n-type dopedsemiconductor materials may be improved when the n-type semiconductormaterial is in a state of tensile stress, and the conductivity of p-typesemiconductor materials may be improved when the p-type semiconductormaterial is in a state of compressive stress.

BRIEF SUMMARY

This summary is provided to introduce a selection of concepts in asimplified form. These concepts are described in further detail in thedetailed description of example embodiments of the disclosure below.This summary is not intended to identify key features or essentialfeatures of the claimed subject matter, nor is it intended to be used tolimit the scope of the claimed subject matter.

In some embodiments, the present disclosure includes a method offabricating a semiconductor structure. A multi-layer substrate isprovided that includes a base substrate, a buried oxide layer over asurface of the base substrate, and a strained semiconductor layer overthe buried oxide layer on a side thereof opposite the base substrate.The strained semiconductor layer comprises crystalline semiconductormaterial. The method further includes implanting ions into a secondregion of the strained semiconductor layer without implanting ions intoa first region of the strained semiconductor layer and converting aportion of the crystalline semiconductor material in the second regionof the strained semiconductor layer to amorphous material such that thesecond region of the strained semiconductor layer has an amorphousregion and an underlying crystalline region. The amorphous region isrecrystallized, and elements are diffused from one portion of the secondregion of the strained semiconductor layer into another portion of thestrained semiconductor layer so as to enrich a concentration of thediffused elements in the another portion of the second region of thestrained semiconductor layer and alter a strain state of the secondregion of the strained semiconductor layer such that the second regionof the strained semiconductor layer is in a strain state differing froma strain state of the first region of the strained semiconductor layer.A first plurality of transistor channel structures are formed that eachcomprise a portion of the first region of the semiconductor layer, and asecond plurality of transistor channel structures are formed that eachcomprise a portion of the second region of the semiconductor layer.

In additional embodiments, the present disclosure includes semiconductorstructures that may be fabricated by methods as disclosed herein. Forexample, in some embodiments, the present disclosure includes asemiconductor structure comprising a base substrate, a buried oxidelayer over a surface of the base substrate, and a first plurality oftransistor channel structures and a second plurality of transistorchannel structures disposed over the buried oxide layer in a commonplane on a side thereof opposite the base substrate. Each transistorchannel structure of the second plurality of transistor channelstructures comprises a condensed strained semiconductor layer includingtwo or more elements. Each transistor channel structure of the firstplurality of transistor channel structures comprises a non-condensedstrained semiconductor layer. The transistor channel structures of thesecond plurality of transistor channel structures have acrystallographic strain differing from a crystallographic strain of thetransistor channel structures of the first plurality of transistorchannel structures.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming what are regarded as embodiments of theinvention, the advantages of embodiments of the disclosure may be morereadily ascertained from the description of certain examples ofembodiments of the disclosure when read in conjunction with theaccompanying drawings, in which:

FIG. 1 is a simplified, schematically illustrated cross-sectional viewillustrating a multi-layer substrate including a strained semiconductorlayer that may be employed in accordance with embodiments of the presentdisclosure;

FIG. 2 illustrates the substrate of FIG. 1 after applying a mask layerover a portion of the multi-layer substrate, and illustratesimplantation of ions into the strained semiconductor layer in anun-masked portion of the multi-layer substrate;

FIG. 3 is an enlarged view of a portion of the substrate of FIGS. 1 and2 showing a portion of the semiconductor layer after implanting ionstherein, such that an amorphous region is formed within thesemiconductor layer;

FIG. 4 is similar to FIG. 3 and illustrates the portion of thesemiconductor layer after recrystallizing the amorphous region therein;

FIG. 5 is similar to FIGS. 3 and 4, and illustrates the portion of thesemiconductor layer after removing an oxide layer from the surface ofthe semiconductor layer;

FIG. 6 is similar to FIGS. 3 through 5, and illustrates the portion ofthe semiconductor layer after epitaxially depositing additionalsemiconductor material on the semiconductor layer so as to thicken thesemiconductor layer;

FIG. 7 is similar to FIGS. 3 through 6 and illustrates the portion ofthe semiconductor layer after diffusing elements from one region thereofinto another region thereof so as to enrich a region of thesemiconductor layer with one or more elements and alter a strain stateof the region of the semiconductor layer;

FIG. 8 is a simplified, schematically illustrated cross-sectional viewillustrating a semiconductor structure fabricated using the methodsdescribed with reference to FIGS. 1-7, which comprises asemiconductor-on-insulator (SeOI) substrate including a semiconductorlayer having regions of different strain states over a buried oxidelayer on a base substrate;

FIG. 9 is a simplified, schematically illustrated cross-sectional viewillustrating a semiconductor structure that may be fabricated from theSeOI substrate of FIG. 8, and includes a first plurality of finstructures formed in a region of the semiconductor layer having a firststrain state, and a second plurality of fin structures formed in aregion of the semiconductor layer having a different second strainstate;

FIG. 10 is a simplified, schematically illustrated cross-sectional viewillustrating another semiconductor structure that may be fabricated fromthe SeOI substrate of FIG. 8, and includes a shallow trench isolationstructure formed between the regions of different strain states;

FIG. 11 is a simplified, schematically illustrated cross-sectional viewillustrating another multi-layer substrate like that of FIG. 1 includinga strained semiconductor layer that may be employed in accordance withembodiments of the present disclosure;

FIG. 12 illustrates a plurality of fin structures formed from thestrained semiconductor layer of the substrate of FIG. 11;

FIG. 13 illustrates implantation of ions into some, but not all of thefin structures;

FIG. 14 is an enlarged view of a portion of the substrate of FIG. 13showing some of the fin structures after implanting ions into the finstructures and forming an amorphous region within the fin structures;

FIG. 15 is similar to FIG. 14 and illustrates the fin structures afterrecrystallizing the amorphous regions therein;

FIG. 16 is similar to FIGS. 14 and 15, and illustrates the finstructures after diffusing elements from one region thereof into anotherregion thereof so as to enrich a region of the fin structures with oneor more elements and alter a strain state of the fin structures; and

FIG. 17 illustrates an example structure of a finFET transistor.

DETAILED DESCRIPTION

The illustrations presented herein are not meant to be actual views ofany particular semiconductor structure, device, system, or method, butare merely idealized representations that are used to describeembodiments of the disclosure.

Any headings used herein should not be considered to limit the scope ofembodiments of the invention as defined by the claims below and theirlegal equivalents. Concepts described in any specific heading aregenerally applicable in other sections throughout the entirespecification.

The terms first and second in the description and the claims are usedfor distinguishing between similar elements.

As used herein, the terms “fin” and “fin structure” mean an elongated,three-dimensional finite and hounded volume of semiconductor materialhaving a length, a width, and a height, wherein the length is greaterthan the width. The width and height of the fin may vary along thelength of the fin in some embodiments.

Described below with reference to the figures are methods that may beused to fabricate semiconductor structures, and semiconductor structuresthat may be fabricated using such methods.

Referring to FIG. 1, a multi-layer substrate 100 may be provided thatincludes a base substrate 102, a buried oxide (BOX) layer 104 over asurface of the base substrate 102, and a strained semiconductor layer106 over the BOX layer 104 on a side thereof opposite the base substrate102. The strained semiconductor layer 106 may comprise a strainedsilicon layer, and the multi-layer substrate 100 may comprise a strainedsilicon-on-insulator (SSOI) substrate.

The base substrate 102 may comprise a die or wafer of, for example,semiconductor material (e.g., silicon, silicon carbide, germanium, aIII-V semiconductor material, etc.), a ceramic material (e.g., siliconoxide, aluminum oxide, silicon carbide, etc.), or a metal material(e.g., molybdenum, etc.). The base substrate 102 may have amonocrystalline or polycrystalline microstructure in some embodiments.In other embodiments, the base substrate 102 may be amorphous. The basesubstrate 102 may have a thickness ranging from, for example, about 400μm to about 900 μm (e.g., about 750 μm), although thicker or thinnerbase substrates 102 may also be employed.

The layers overlying the base substrate 102, such as the BOX layer 104,may be deposited, “grown,” or otherwise formed over the substrateepitaxially using any of a number of different processes such as, forexample, chemical vapor deposition (CVD), atomic layer deposition (ALD),physical vapor deposition (PLD), vapor phase epitaxy (VPE), molecularbeam epitaxy (MBE) and thermal oxidation. In additional embodiments,they may be transferred to the base substrate 102 from another donorsubstrate using known processes.

By way of example and not limitation, the multi-layer substrate 100 maybe formed using the process known in the art as the SMART-CUT® process,in which a layer of semiconductor material is transferred from a donorstructure to receiving substrate (i.e., the base substrate) such that anoxide layer (i.e., the BOX layer 104) is disposed between the receivingsubstrate and the transferred layer semiconductor layer. The SMART-CUT®process is described in, for example, U.S. Pat. No. RE 39,484 to Bruel(issued Feb. 6, 2007), U.S. Pat. No. 6,303,468 to Aspar et al. (issuedOct. 16, 2001), U.S. Pat. No. 6,335,258 to Aspar et al. (issued Jan. 1,2002), U.S. Pat. No. 6,756,286 to Moriceau et al. (issued Jun. 29,2004), U.S. Pat. No. 6,809,044 to Aspar et al. (issued Oct. 26, 2004),and U.S. Pat. No. 6,946,365 to Aspar et al. (Sep. 20, 2005), thedisclosures of which are incorporated herein in their entireties by thisreference.

The BOX layer 104 may comprise, for example, an oxide (e.g., silicondioxide, aluminum oxide, hafnium oxide, etc.), a nitride (e.g., siliconnitride), an oxynitride (e.g., silicon oxynitride), or a combination ofsuch dielectric materials. The BOX layer 104 may be crystalline oramorphous. The BOX layer 104 may have an average layer thickness of, forexample, between about 10 nm and about 200 nm, although thicker orthinner BOX layers 104 may also be employed in embodiments of thepresent disclosure.

The strained semiconductor layer 106 may comprise a strained(compressive or tensile) crystalline semiconductor material, such as alayer of tensile strained silicon (Si). In other embodiments, thestrained semiconductor layer 106 may comprise strained germanium (Ge),strained silicon germanium (SiGe), or a strained III-V semiconductormaterial. Thus, the strained semiconductor material 106 may have acrystal structure exhibiting lattice parameters that are either above(tensile strained) or below (compressively strained) the relaxed latticeparameters that would normally be exhibited by the crystal structure ofthe respective semiconductor material in free-standing, bulk form atequilibrium state. The strained semiconductor layer 106 may have anaverage layer thickness of about 50 nm or less, or even about 10 nm orless. The strained semiconductor layer 106 may have an average layerthickness below a critical thickness of the strained semiconductor layer106. In embodiments in which the strained semiconductor layer 106comprises a strained silicon layer that is transferred to the basesubstrate 102 from a donor substrate, and wherein the strainedsemiconductor layer 106 is epitaxially grown on a SiGe buffer layer onthe donor substrate prior to the layer transfer process, the criticalthickness of the strained silicon layer may be a function of thegermanium concentration in the SiGe buffer layer, with the criticalthickness decreasing with increasing germanium concentration. Thickerlayers of strained semiconductor material 106 may also be employed inembodiments of the present disclosure. The strained semiconductor layer106 may be thickened to a thickness greater than its critical thickness,after transfer thereof to the base substrate 102, without degradingstrain relaxation using epitaxy deposition techniques as disclosed in,for example, Thean et al., Stress Hybridization for Super-CriticalStrained-Si Directly On Insulator (SC-SSOI) PMOS With Different ChannelOrientations, IEEE International (Electron Devices Meeting, Washington,D.C. 2005), pages 509-512, which is incorporated herein in its entiretyby this reference.

As a non-limiting specific example, the base substrate 102 of the donorsubstrate 100 may comprise a monocrystalline silicon substrate, the BOXlayer 104 may comprise silicon dioxide (SiO₂), and the strainedsemiconductor layer 106 may comprise tensile strained monocrystallinesilicon (sSi) having a thicknesses below its respective criticalthickness so as to avoid the onset of relaxation and formation oflocalized defects in the crystal structure thereof.

In some embodiments, an oxide layer 108, which may be a native oxidelayer or deposited oxide, may be present over the major surface of thestrained semiconductor layer 106 on the side thereof opposite the BOXlayer 104. In other embodiments, the oxide layer 108 may not be present.

Referring to FIG. 2, a patterned mask layer 110 may be provided over thestrained semiconductor layer 106. The patterned mask layer 110 may coverone or more regions of the strained semiconductor layer 106, while otherregions of the strained semiconductor layer 106 may be uncovered by thepatterned mask layer 110. As a non-limiting example, FIG. 2 illustratesa first region of the strained semiconductor layer 106A that is coveredby the patterned mask layer 110, and a second region of the strainedsemiconductor layer 106B that is uncovered by the patterned mask layer110.

The patterned mask layer 110 may comprise a hard mask layer material,such as one or more of an oxide layer, a nitride layer, or an oxynitridelayer. The patterned mask layer 110 may be formed by depositing orotherwise providing a continuous layer of hard mask material over themulti-layer substrate 100, and subsequently patterning the hard maskmaterial using a photolithographic masking and etching process to formapertures through the hard mask material at the locations at which it isdesired to remove portions of the hard mask material to uncover regionsof the strained semiconductor layer 106. In other embodiments, thepatterned mask layer 110 may comprise a photoresist masking material.

With continued reference to FIG. 2, after forming the patterned masklayer 110, ions may be implanted into the region or regions of thestrained semiconductor layer 106 that are uncovered by the patternedmask layer 110 (as indicated by the directional arrows), such as thesecond region of the strained semiconductor layer 106B, withoutimplanting ions into the region or regions of the strained semiconductorlayer 106 that are covered by the patterned mask layer 110, such as thefirst region of the strained semiconductor layer 106A. The ions may passthrough the apertures in the mask layer 110 and into the first region ofthe strained semiconductor layer 106A, while the mask layer 110 shieldsthe second region of the strained semiconductor layer 106B and preventsthe ions from being implanted therein.

In some embodiments, the oxide layer 108, if present, may be removedfrom over the strained semiconductor layer 106 such that a surface ofthe strained semiconductor layer 106 is exposed. In other embodiments,however, the ions may be implanted into the strained semiconductor layer106 through the oxide layer 108.

The implantation of the ions may convert a portion of the crystallinesemiconductor material of the strained semiconductor layer 106 toamorphous material. Thus, the region or regions of the semiconductorlayer 106 into which the ions are implanted may have an amorphous region112 and an underlying crystalline region 114, as illustrated in theenlarged view of FIG. 3.

The implanted ions may be ions of elements different from at least oneelement present in the crystal structure of the semiconductor layer 106.For example, in embodiments in which the strained semiconductor layercomprises strained silicon (sSi), the implanted ions may comprise, forexample, germanium ions, which are different from silicon. The reasonfor this, is that the implanted ions, having a different atomic radiirelative to other elements in the semiconductor layer 106, may be usedto subsequently alter a strain state of the semiconductor layer 106 insubsequent processing as described in further detail below.

Table 1 below provides examples of germanium concentration and germaniumcontent in a tensile strained silicon semiconductor layer 106 at layerthicknesses of the semiconductor layer 106, for each of five (5)different dosages of a germanium ion implantation process performed withion implant energies of 40-50 KeV.

TABLE 1 Ge Implant Dose Ge COnc. Si Layer Dose No. (at · cm−2) (at ·cm−3) Ge Content Thickness (1) 1.00E+15 1.00E+19 0.02% 100 nm  (2)5.00E+15 5.00E+19 0.10% (3) 1.00E+16 1.00E+20 0.20% (4) 5.00E+165.00E+20 1.00% (5) 1.00E+17 1.00E+21 2.00% (1) 1.00E+15 2.00E+19 0.04%50 nm (2) 5.00E+15 1.00E+20 0.20% (3) 1.00E+16 2.00E+20 0.40% (4)5.00E+16 1.00E+21 2.00% (5) 1.00E+17 2.00E+21 4.00% (1) 1.00E+153.33E+19 0.07% 30 nm (2) 5.00E+15 1.67E+20 0.33% (3) 1.00E+16 3.33E+200.67% (4) 5.00E+16 1.67E+21 3.33% (5) 1.00E+17 3.33E+21 6.67% (1)1.00E+15 5.00E+19 0.10% 20 nm (2) 5.00E+15 2.50E+20 0.50% (3) 1.00E+165.00E+20 1.00% (4) 5.00E+16 2.50E+21 5.00% (5) 1.00E+17 5.00E+21 10.00%(1) 1.00E+15 1.00E+20 0.20% 10 nm (2) 5.00E+15 5.00E+20 1.00% (3)1.00E+16 1.00E+21 2.00% (4) 5.00E+16 5.00E+21 10.00% (5) 1.00E+171.00E+22 20.00%

Referring to FIG. 4, after implanting the ions into the region orregions of the strained semiconductor layer 106 such that the region orregions include an amorphous region 112 and an underlying crystallineregion 114 (as shown in FIG. 3), the amorphous regions 112 of thesemiconductor layer 106 may be recrystallized. For example, an annealingprocess carried out in a furnace at elevated temperatures may be used torecrystallize the amorphous regions 112 and form recrystallized regions120, as shown in FIG. 4. Upon recrystallization, the recrystallizedregions 120 may be in a strain state that is different from a strainstate of the first region of the strained semiconductor layer 106A (FIG.2), due to the presence of the implanted ions (e.g., germanium ions)having a different atomic radii relative to at least one element (e.g.,silicon) present in semiconductor layer 106 as initially formed.

Thus, in embodiments in which the strained semiconductor layer 106 asinitially formed comprises tensile strained silicon, and the implantedions comprise germanium ions, the recrystallized regions 120 maycomprise Si_(y)Ge_(1-y), wherein y is from about 0.01 to about 0.50, orfrom about 0.10 to about 0.20 in some embodiments.

During the recrystallization process, the recrystallization of theamorphous regions 112 of the semiconductor layer 106 may be seeded bythe underlying crystalline regions 114 of the semiconductor layer 106.Since the underlying crystalline region 114 of the semiconductor layer106 may comprise silicon and the recrystallized regions 120 may compriseSi_(y)Ge_(1-y), the recrystallized regions 114 of Si_(y)Ge_(1-y) formupon the underlying Si, and the crystal lattice of the Si_(y)Ge_(1-y)may be constrained by the underlying Si, such that the recrystallizedregions of Si_(y)Ge_(1-y) are in a state of compressive strain (thelattice parameters of Si_(y)Ge_(1-y) being greater than the latticeparameters of Si, since the atomic radius of Ge is larger than that ofSi).

Referring to FIG. 5, after recrystallizing the amorphous regions 112 ofthe semiconductor layer 106 to form the recrystallized regions 120, theoptional oxide layer 108, if present, may be removed using one or moreof a chemical etching process, a mechanical polishing process, or achemical-mechanical polishing (CMP) process.

As shown in FIG. 6, in some embodiments, additional semiconductormaterial 124 may be selectively epitaxially grown on the second regionof the semiconductor layer 106B without epitaxially growing additionalsemiconductor material on the first region of the semiconductor layer106A. The additional semiconductor material 124 may comprise silicon orSi_(1-y)Ge_(y), for example.

In some embodiments, the growth of the additional semiconductor material124 may be carried out after recrystallizing the amorphous regions 112to form the recrystallized regions 120, as illustrated in the sequenceof the figures. In other embodiments, however, the growth of theadditional semiconductor material 124 may be carried out prior toimplanting ions into the second region of the semiconductor layer 106Band forming the amorphous regions 112 (FIG. 3). The selective epitaxialgrowth of additional semiconductor material 124 as discussed in relationto FIG. 6, when performed prior to the ion implantation processdescribed with reference to FIG. 2, may also enable the implantation ofa higher quantity of ions, which may allow for attaining higherconcentrations of the implanted ions in the second region of thesemiconductor layer 106B, as well as performance of a longer thermaldiffusion process as described below with reference to FIG. 7, and,hence, a larger degree of alteration of a strain state of the secondregion of the semiconductor layer 106B.

The thickness of the additional semiconductor material 124 selectivelyepitaxially grown over the second region of the semiconductor layer 106Bmay be selected such that, subsequent to a diffusion and enrichmentprocess described below with reference to FIG. 7, a thickness of thesecond region of the semiconductor layer 106B may be at leastsubstantially equal to a thickness of the first region of thesemiconductor layer 106A, which is not subjected to the diffusion andenrichment process described with reference to FIG. 7.

Referring to FIG. 7, after recrystallizing the amorphous regions 112 ofthe second region of the semiconductor layer 106B to form therecrystallized regions 120, elements may be diffused from one portion ofthe recrystallized regions 120 of the second region of the semiconductorlayer 106B into another portion of the second region of thesemiconductor layer 106B so as to enrich a concentration of the diffusedelements in the another portion of the second region of thesemiconductor layer 106B and alter a strain state of the second regionof the semiconductor layer 106B.

For example, a condensation process (often referred to as a “thermalmixing” process) or another type of process may be used to diffuseelements within the second region of the semiconductor layer 106B suchthat they are concentrated and enriched within a portion of the secondregion of the semiconductor layer 106B so as to selectively reducetensile strain, increase compressive strain, and/or relax the strain inthe second region of the semiconductor layer 106B relative to the levelof strain in the first region of the semiconductor layer 106A. In suchembodiments, the elements may not be diffused in any substantial mannerwithin the first region of the semiconductor layer 106A. In other words,the condensation process may be carried out only on the second region ofthe semiconductor layer 106B, but not the first region of thesemiconductor layer 106A. Such a condensation process is describedbelow.

FIG. 7 is similar to FIGS. 3 through 6 and illustrates the multi-layersubstrate 100 after carrying out a condensation process on the secondregion of the semiconductor layer 106B. The condensation process mayinvolve subjecting the second region of the semiconductor layer 106B toan oxidation process in a furnace at elevated temperatures (e.g., aboutbetween about 900° C. and about 1150° C.) in an oxidizing atmosphere(e.g., dry O₂ with or without HCL). The oxidation process may result inthe formation of an oxide layer 122 at the surface of the second regionof the semiconductor layer 106B, and may cause diffusion of elementsfrom within an upper region of the second region of the semiconductorlayer 106B into a lower region of the second region of the semiconductorlayer 106B.

In embodiments in which the strained semiconductor layer 106 comprisesstrained silicon (sSi), the ions implanted into the second region of thesemiconductor layer 106B as described with reference to FIG. 2 maycomprise germanium ions, and the germanium atoms may diffuse furtherinto the second region of the semiconductor layer 106B during thecondensation process. An oxide layer 122 may form at the surface of thesecond region of the semiconductor layer 106B and grow in thickness intothe second region of the semiconductor layer 106B. As the thickness ofthe oxide layer 122 grows during the germanium condensation process, thethickness of the Si_(y)Ge_(1-y) semiconductor layer 106 decreases, andthe concentration of germanium in the semiconductor layer 106 increasesuntil the Si_(y)Ge_(1-y), semiconductor layer 106 has a desiredconcentration of germanium therein. The diffusion and concentration ofgermanium within the second region of the semiconductor layer 106B mayresult in a decrease in any tensile strain within the strainedsemiconductor layer 106, and may lead to relaxation of the strain and/orgeneration of compressive strain within the strained semiconductor layer106.

As a result, the first region of the semiconductor layer 106A may be ina first strain state and the second region of the semiconductor layer106B may be in a second strain state differing from the first strainstate.

The oxide layer 122 formed in the diffusion and enrichment process(e.g., condensation process) may be removed form over the second regionof the semiconductor layer 106B prior to subsequent processing.

As previously mentioned, the first region of the semiconductor layer106A may comprise a tensile strained silicon layer. The tensile strainin the first region of the semiconductor layer 106A may provide improvedelectron mobility within the first region of the semiconductor layer106A, which may be desirable for forming n-type FET transistors havingchannel regions comprising portions of the first region of thesemiconductor layer 106A. The ion-implantation and recrystallizationprocess, as well as the condensation process, performed in the secondregion of the semiconductor layer 106B may result in improved holemobility within the second region of the semiconductor layer 106B, whichmay be desirable for forming p-type FET transistors having channelregions comprising portions of the second region of the semiconductorlayer 106B.

As shown in FIG. 8, the oxide layer 108 and the mask layer 110 overlyingthe semiconductor layer 106 may be removed to form a semiconductorstructure 130. The semiconductor structure 130 shown in FIG. 8, which isformed by the methods as described with reference to FIGS. 1-7, includesa base substrate 102, a BOX layer 108 over a surface of the basesubstrate 102, and a first region of a semiconductor layer 106A and asecond region of a semiconductor layer 106B disposed over the BOX layer104 in a common plane on a side of the BOX layer 104 opposite the basesubstrate 102. The semiconductor structure 130 may be subsequentlyprocessed to complete fabrication of a semiconductor device includingboth n-type and p-type transistors. The n-type transistors may be formedon and/or in the first region of the semiconductor layer 106, and thep-type transistors may be formed on and/or in the second region of thesemiconductor layer 106.

FIG. 9, for example, illustrates for formation of a first plurality offin structures 132A each comprising a portion of the first region of thesemiconductor layer 106A, and a second plurality of fin structures 132Beach comprising a portion of the second region of the semiconductorlayer 106B. Each of the fin structures 132A, 132B is sized andconfigured for use as a transistor channel structure in finFET typetransistors. As a non-limiting example, each of the fin structures 132A,132B may be formed to have an average width of about 15 nm or less.

The fin structures 132B of the second plurality of fin structures 132Bhave a crystallographic strain differing from a crystallographic strainof the fin structures 132A of the first plurality of fin structures132A. Each fin structure 132A of the first plurality of fin structures132A includes a non-condensed strained semiconductor material. Each finstructure 132B of the second plurality of fin structures 132B includes acondensed strained semiconductor material including two or more elements(e.g., silicon and germanium).

After forming the first and second pluralities of fin structures 132A,132B, a first plurality of n-type finFET transistors may be formedcomprising the first plurality of fin structures 132A, and a secondplurality of p-type finFET transistors may be formed comprising thesecond plurality of fin structures 132B.

In additional embodiments, the semiconductor structure 130 of FIG. 8 maybe subsequently processed to form a plurality of conventional planarn-type metal-oxide semiconductor field effect transistors (NMOS FETs) onand/or in the first region of the semiconductor layer 106A, and aplurality of conventional planar p-type metal-oxide semiconductor fieldeffect transistors (PMOS FETs) on and/or in the second region of thesemiconductor layer 106B, as illustrated in FIG. 10. For example, one ormore shallow trench isolation (STI) structures 134 may be formedpartially or entirely through the semiconductor layer 106 so as toelectrically isolate transistor channel regions to be formed in thesemiconductor layer 106. Conventional STI processing may be used todefine transistor channel structures in the semiconductor layer 106. Insuch processing, a masking and etching process may be used to formtrenches between the adjacent transistor channel structures, anddielectric material may be provided within the trenches to form STIstructures 134 between the transistor channel structures. Thus, the STIstructures 134 in the semiconductor layer 106 may be used toelectrically isolate the transistor channel structures to be defined inthe semiconductor layer 106. Although only one STI structure 134 isillustrated in FIG. 10, a plurality of such STI structures 134 may beused to define the transistor channel structures in the semiconductorlayer 106.

After forming the STI structures 134 in the semiconductor layer 106, afirst plurality of transistor channel structures may be foamed that eachcomprise a portion of the first region of the semiconductor layer 106A,and a second plurality of transistor channel structures may be formedthat each comprise a portion of the second region of the semiconductorlayer 106B. The transistor channel structures may be sized andconfigured for use as transistor channel structures in MOS FET typetransistors.

The NMOS FET transistor channel structures formed in the first region ofthe semiconductor layer 106A have a crystallographic strain differingfrom a crystallographic strain of the PMOS FET transistor channelstructures formed in the second region of the semiconductor layer 106B.After forming the first and second pluralities of transistor channelstructures, a first plurality of NMOS FET transistors may be formedcomprising the first plurality of transistor channel structures, and asecond plurality of PMOS FET transistors may be formed comprising thesecond plurality of transistor channel structures.

In additional embodiments, a first plurality of NMOS FET transistors maybe formed comprising the first plurality of transistor channelstructures, and a second plurality of PMOS FET transistors may be formedcomprising the second plurality of transistor channel structures, priorto forming the STI structures 134. FIGS. 11 through 16 illustrate anadditional embodiment of a method that may be used to fabricateco-planar n-type and p-type finFET transistors similar to that describedabove with reference to FIGS. 1 through 9.

FIG. 11 illustrates a multi-layer substrate 140 that includes a basesubstrate 102, a buried oxide layer 104, and a strained semiconductorlayer 106 as previously described herein with reference to FIG. 1.

As shown in FIG. 12, the strained semiconductor layer 106 may bepatterned using, for example, a masking and etching process to form finstructures 142 each comprising a region of the strained semiconductorlayer 106. The fin structures 142 may be formed using finFET fabricationprocesses known in the art, and may include Spacer-Defined DoublePatterning (SDDP) processes (also known in the art as “Side-wall ImageTransfer” processes). The fin structures 142 may include a secondplurality of fin structures 142B and a first plurality of fin structures142A.

Referring to FIG. 13, one or more masking layers may be deposited overthe fin structures 142. The masking layers may include, for example, apassivating oxide layer 144, a nitride layer 146, and a mask layer 148.The mask layer 148 may comprise, for example, a photoresist maskingmaterial, which may be patterned to form apertures therethrough over thesecond plurality of fin structures 142B. One or both of the oxide layer144 and the nitride layer 146 may be removed using one or more etchingprocesses, in which they are exposed to an etchant through the aperturesin the mask layer 148 while the mask layer 148 shields the remainder ofthe structure from the etchant. As shown in FIG. 13, in someembodiments, regions of the nitride layer 146 overlying the secondplurality of fin structures 142B may be removed using an etchingprocess, while at least a portion of the oxide layer 144 may be left inplace over the second plurality of fin structures 142B. In otherembodiments, however, the portions of the oxide layer 144 overlying thesecond plurality of fin structures 142B may be at least substantiallycompletely removed. The mask layer 148 optionally may be removed priorto subsequent processing, or the mask layer 148 may be left in place asshown in FIG. 13.

As shown in FIG. 13, ions may be implanted into the second plurality offin structures 142B through the apertures in one or both of the masklayer 148 and the nitride layer 146 in a process as previously describedwith reference to FIG. 2 so as to form amorphous regions 150 in portionsof the second plurality of fin structures 142B, as shown in FIG. 14. Thesecond plurality of fin structures 142B may include crystalline regions152 of the strained semiconductor layer 106 remaining under theamorphous regions 150, substantially as previously described withreference to FIG. 3.

Referring to FIG. 15, after forming the amorphous regions 150, theamorphous regions 150 may be recrystallized to form recrystallizedregions 154. The recrystallization process may be carried out aspreviously described with reference to FIG. 4.

Referring to FIG. 16, a diffusion and enrichment process (e.g., acondensation process) may be carried out on the second plurality of finstructures 142B in a manner as previously described with reference toFIG. 7 after forming the recrystallized regions 154 (FIG. 15). Thediffusion and enrichment process may result in the formation of an oxidelayer 156 over each of the fin structures 142B of the second plurality.

Optionally, epitaxial growth of additional semiconductor material alsomay be carried out on the second plurality of fin structures 142B priorto performing the diffusion and enrichment process, as previouslydescribed with reference to FIGS. 5 and 6.

Thus, the second plurality of fin structures 142B may comprisetransistor channel structures sized and configured for forming p-typefinFET transistors, and the first plurality of fin structures 142A maycomprise transistor channel structures sized and configured for formingn-type finFET transistors.

After forming the first and second pluralities of fin structures 142A,142B as previously described with reference to FIGS. 11-16, a firstplurality of NMOS finFET transistors may be formed comprising the firstplurality of fin structures 142A, and a second plurality of PMOS finFETtransistors may be formed comprising the second plurality of finstructures 142B.

FIG. 17 illustrates a non-limiting simplified example embodiment of afinFET transistor configuration that may be fabricated using the secondplurality of fin structures 142B and/or the first plurality of finstructures 142A in accordance with embodiments of the present disclosure(of the fin structures of FIG. 9). It should be noted that manydifferent configurations of finFETs are known in the art and may beemployed in accordance with embodiments of the disclosure, and thefinFET structure shown in FIG. 17 is set forth merely as an example ofsuch finFET structures.

As shown in FIG. 17, a finFET transistor 160 comprises a source region162, a drain region 164, and a channel extending between the sourceregion 162 and the drain region 164. The channel is defined by andcomprises a fin, such as either a first fin structure 142A or a secondfin structure 142B. In some embodiments, the source region 162 and thedrain region 164 may include, or be defined by, longitudinal endportions of a fin structure 142. A conductive gate 166 extends over andadjacent at least a portion of the fin structure 142 between the sourceregion 162 and the drain region 164. The gate 166 may be separated fromthe fin structure 142 by a dielectric material 168. The gate 166 mayinclude a multilayer structure, and may include semiconductive and/orconductive layers. A low-resistance layer including a metal, a metalcompound or both, such as a conductive silicide, may be deposited overthe source region 162 and/or the drain region 164 to form electricalcontacts therewith.

Advantageously, tensile stress/strain in the channel can increase theperformance of NMOS finFET transistors and reduce the threshold voltage,while reduced tensile stress/strain (e.g., less tensile stress, notensile or compressive stress, or compressive stress) in the channel canincrease the performance of PMOS finFET transistors and reduce thethreshold voltage. For some functions, strained devices are beneficialbecause high performance is needed, and for some other functions,performance is not as important, but a high threshold voltage isbeneficial. With embodiments of the present disclosure, the manufacturercan selectively incorporate differing levels of stress and strain intothe crystal lattices of different finFET or MOSFET transistors in thesame device in a common FET transistor plane.

Additional, non-limiting example embodiments of the disclosure are setforth below.

Embodiment 1: A method of fabricating a semiconductor structure,comprising: providing a multi-layer substrate, including: a basesubstrate, a buried oxide layer over a surface of the base substrate,and a strained semiconductor layer over the buried oxide layer on a sidethereof opposite the base substrate, the strained semiconductor layercomprising crystalline semiconductor material; implanting ions into asecond region of the strained semiconductor layer without implantingions into a first region of the strained semiconductor layer andconverting a portion of the crystalline semiconductor material in thesecond region of the strained semiconductor layer to amorphous materialsuch that the second region of the strained semiconductor layer has anamorphous region and an underlying crystalline region; recrystallizingthe amorphous region; diffusing elements from one portion of the secondregion of the strained semiconductor layer into another portion of thestrained semiconductor layer so as to enrich a concentration of thediffused elements in the another portion of the second region of thestrained semiconductor layer and alter a strain state of the secondregion of the strained semiconductor layer such that the second regionof the strained semiconductor layer is in a strain state differing froma strain state of the first region of the strained semiconductor layer;and forming a first plurality of transistor channel structures eachcomprising a portion of the first region of the semiconductor layer anda second plurality of transistor channel structures each comprising aportion of the second region of the semiconductor layer.

Embodiment 2: The method of Embodiment 1, further comprising selectingthe strained semiconductor layer to comprise strained silicon.

Embodiment 3: The method of Embodiment 2, further comprising selectingthe strained semiconductor layer to comprise tensile strained silicon.

Embodiment 4: The method of Embodiment 2 or Embodiment 3, whereinimplanting ions into the second region of the strained semiconductorlayer comprises implanting germanium ions into the second region of thestrained semiconductor layer to form Si_(y)Ge_(1-y), wherein y is fromabout 0.10 to about 0.50, and wherein diffusing elements from oneportion of the second region of the strained semiconductor layer intoanother portion of the strained semiconductor layer comprises diffusinggermanium into the another portion of the second region of the strainedsemiconductor layer.

Embodiment 5: The method of any one of Embodiments 1 through 4, whereinforming the first plurality of transistor channel structures and thesecond plurality of transistor channel structures comprises forming afirst plurality of fin structures each comprising a portion of the firstregion of the semiconductor layer and a second plurality of finstructures each comprising a portion of the second region of thesemiconductor layer.

Embodiment 6: The method of Embodiment 5, further comprising forming aplurality of n-type FinFET transistors comprising the first plurality offin structures and forming a plurality of p-type FinFET transistorscomprising the second plurality of fin structures.

Embodiment 7: The method of any one of Embodiments 1 through 6, furthercomprising forming the transistor channel structures of the first andsecond pluralities of transistor channel structures to have an averagewidth of about 15 nm or less.

Embodiment 8: The method of any one of Embodiments 1 through 7, whereindiffusing elements from one portion of the second region of the strainedsemiconductor layer into another portion of the strained semiconductorlayer comprises relaxing strain in the second region of the strainedsemiconductor layer.

Embodiment 9: The method of Embodiment 8, wherein relaxing strain in thesecond region of the strained semiconductor layer comprises increasing ahole mobility within the second region of the strained semiconductorlayer.

Embodiment 10: The method of any one of Embodiments 1 through 9, whereindiffusing elements from one portion of the second region of the strainedsemiconductor layer into another portion of the strained semiconductorlayer comprises carrying out a condensation process on the second regionof the strained semiconductor layer.

Embodiment 11: The method of Embodiment 10, wherein carrying out acondensation process on the second region of the strained semiconductorlayer comprises oxidizing a portion of the second region of the strainedsemiconductor layer.

Embodiment 12: The method of any one of Embodiments 1 through 11,wherein recrystallizing the amorphous region comprises seedingrecrystallization of the amorphous region with the underlyingcrystalline region.

Embodiment 13: The method of any one of Embodiments 1 through 12,further comprising epitaxially growing additional semiconductor materialon the second region of the semiconductor layer without growingadditional semiconductor material on the first region of thesemiconductor layer prior to diffusing elements from one portion of thesecond region of the strained semiconductor layer into the anotherportion of the strained semiconductor layer.

Embodiment 14: A semiconductor structure, comprising: a base substrate,a buried oxide layer over a surface of the base substrate, a firstplurality of transistor channel structures and a second plurality oftransistor channel structures disposed over the buried oxide layer in acommon plane on a side thereof opposite the base substrate, eachtransistor channel structure of the second plurality of transistorchannel structures comprising a condensed strained semiconductor layerincluding two or more elements, each transistor channel structure of thefirst plurality of transistor channel structures comprising anon-condensed strained semiconductor layer; wherein the transistorchannel structures of the second plurality of transistor channelstructures have a crystallographic strain differing from acrystallographic strain of the transistor channel structures of thefirst plurality of transistor channel structures.

Embodiment 15: The semiconductor structure of Embodiment 14, wherein thenon-condensed strained semiconductor layer of each transistor channelstructure of the first plurality of transistor channel structurescomprises strained silicon.

Embodiment 16: The semiconductor structure of Embodiment 14 orEmbodiment 15, wherein the condensed strained semiconductor layer ofeach transistor channel structure of the second plurality of transistorchannel structures comprises Si_(x)Ge_(1-x), wherein x is from about0.01 to about 0.50.

Embodiment 17: The semiconductor structure of any one of Embodiments 14through 16, wherein the transistor channel structures of the firstplurality of transistor channel structures are in a state of tensilestrain and the transistor channel structures of the first plurality oftransistor channel structures are relaxed or in a state of compressivestrain.

Embodiment 18: The semiconductor structure of any one of Embodiments 14through 17, wherein the transistor channel structures of the firstplurality of transistor channel structures and the second plurality oftransistor channel structures have an average width of about 15 nm orless.

Embodiment 19: The semiconductor structure of any one of Embodiments 14through 18, wherein the transistor channel structures of each of thefirst plurality of transistor channel structures and the secondplurality of transistor channel structures comprise fin structures.

Embodiment 20: The semiconductor structure of Embodiment 19, furthercomprising a first plurality of n-type FinFET transistors comprising thefirst plurality of transistor channel structures, and a second pluralityof p-type FinFET transistors comprising the second plurality oftransistor channel structures.

The example embodiments of the disclosure described above do not limitthe scope of the invention, since these embodiments are merely examplesof embodiments of the invention, which is defined by the scope of theappended claims and their legal equivalents. Any equivalent embodimentsare intended to be within the scope of this invention. Indeed, variousmodifications of the disclosure, in addition to those shown anddescribed herein, such as alternate useful combinations of the elementsdescribed, will become apparent to those skilled in the art from thedescription. In other words, one or more features of one exampleembodiment described herein may be combined with one or more features ofanother example embodiment described herein to provide additionalembodiments of the disclosure. Such modifications and embodiments arealso intended to fall within the scope of the appended claims.

1. A semiconductor structure, comprising: a base substrate, a buriedoxide layer over a surface of the base substrate, a first plurality oftransistor channel structures and a second plurality of transistorchannel structures disposed over the buried oxide layer in a commonplane on a side thereof opposite the base substrate, each transistorchannel structure of the second plurality of transistor channelstructures comprising a condensed strained semiconductor layer includingtwo or more elements, each transistor channel structure of the firstplurality of transistor channel structures comprising a non-condensedstrained semiconductor layer; wherein the transistor channel structuresof the second plurality of transistor channel structures have acrystallographic strain differing from a crystallographic strain of thetransistor channel structures of the first plurality of transistorchannel structures.
 2. The semiconductor structure of claim 1, whereinthe non-condensed strained semiconductor layer of each transistorchannel structure of the first plurality of transistor channelstructures comprises strained silicon.
 3. The semiconductor structure ofclaim 1, wherein the condensed strained semiconductor layer of eachtransistor channel structure of the second plurality of transistorchannel structures comprises Si_(x)Ge_(1-x), wherein x is from about0.01 to about 0.50.
 4. The semiconductor structure of claim 1, whereinthe transistor channel structures of the first plurality of transistorchannel structures are in a state of tensile strain and the transistorchannel structures of the first plurality of transistor channelstructures are relaxed or in a state of compressive strain.
 5. Thesemiconductor structure of claim 1, wherein the transistor channelstructures of the first plurality of transistor channel structures andthe second plurality of transistor channel structures have an averagewidth of about 15 nm or less.
 6. The semiconductor structure of claim 1,wherein the transistor channel structures of each of the first pluralityof transistor channel structures and the second plurality of transistorchannel structures comprise fin structures.
 7. The semiconductorstructure of claim 6, further comprising a first plurality of n-typeFinFET transistors comprising the first plurality of transistor channelstructures, and a second plurality of p-type FinFET transistorscomprising the second plurality of transistor channel structures.
 8. Thesemiconductor structure of claim 3, wherein the condensed strainedsemiconductor layer of each transistor channel structure of the secondplurality of transistor channel structures comprises Si_(x)Ge_(1-x),wherein x is from about 0.10 to about 0.20.
 9. The semiconductorstructure of claim 4, wherein the transistor channel structures of thefirst plurality of transistor channel structures are relaxed.
 10. Thesemiconductor structure of claim 4, wherein the transistor channelstructures of the first plurality of transistor channel structures arein a state of compressive strain.
 11. The semiconductor structure ofclaim 2, wherein the condensed strained semiconductor layer of eachtransistor channel structure of the second plurality of transistorchannel structures comprises Si_(x)Ge_(1-x), wherein x is from about0.01 to about 0.50.
 12. The semiconductor structure of claim 11, whereinthe transistor channel structures of the first plurality of transistorchannel structures are in a state of tensile strain and the transistorchannel structures of the first plurality of transistor channelstructures are relaxed or in a state of compressive strain.
 13. Thesemiconductor structure of claim 12, wherein the transistor channelstructures of the first plurality of transistor channel structures andthe second plurality of transistor channel structures have an averagewidth of about 15 nm or less.
 14. The semiconductor structure of claim12, wherein the transistor channel structures of each of the firstplurality of transistor channel structures and the second plurality oftransistor channel structures comprise fin structures.
 15. Thesemiconductor structure of claim 14, further comprising a firstplurality of n-type FinFET transistors comprising the first plurality oftransistor channel structures, and a second plurality of p-type FinFETtransistors comprising the second plurality of transistor channelstructures.
 16. The semiconductor structure of claim 1, wherein the basesubstrate comprises silicon.
 17. The semiconductor structure of claim 1,wherein the buried oxide layer comprises silicon dioxide.